Traditional processors mostly have the same data port for both input and output. Thus, the read/write enable allows the processor data port to either only have the data to output or the data to input as the input and output data ports are multiplexed on the same bus lines. This results in lower performance and lower throughput in the processors.
Thus, came into existence processors which have separated input and output data ports in order to increase the performance and throughput of the processors. The input and output data ports mostly have a separated address value for mapping the input and output data ports. This results in a large number of bits used for the address mapping, thus, making the instruction code word to be longer as different bits are used for indicating the location address for both the input data ports and the output data ports.
Therefore, in light of the above, there is a need for an improved ASIP architecture for input data ports and output data ports that are on separate bus lines.